Contemporary CMOS technologies employ field effect transistors that are adjacent or bounded by trenches. The trenches are used for shallow trench isolation (STI) or they provide a location for trench capacitors.
Parasitic leakage paths have been created by the proximity of a semiconductor device to an edge or comer of either type of trench. In one leakage mechanism, described in a paper, "Process and Device Simulation of Trench Isolation Corner Parasitic Device," by T. Furukawa and J. A. Mandelman, Proceedings of the Electrochemical Society Meeting, Oct. 9-14, 1988, the parasitic leakage path results from an enhancement of the gate electric field near the trench comer. The electric field is enhanced by the comer's small radius of curvature and the proximity of the gate conductor. Processing can exacerbate the problem by sharpening the comer and thinning the gate dielectric near the corner. In addition, in a worst case scenario for comer field enhancement, the gate conductor wraps around the trench corner. This happens when the oxide fill in the isolation trench is recessed below the silicon surface during oxide etches following its formation.
As a result of the enhanced field, the corner has a lower threshold voltage (Vt) than the planar portion of the device. Thus, a parallel path for current conduction is formed. However, for device widths used in contemporary technologies, the top planar portion of the device carries most of the on-current. Trench corner conduction is a parasitic which usually contributes appreciably only to sub-threshold leakage. This parasitic leakage current along the corner is most easily seen as a hump in the subthreshold current curve of a narrow MOSFET.
As described in a paper, "The Current-Carrying Comer Inherent to Trench Isolation," by Andres Bryant, W. Haensch, S. Geissler, Jack Mandelman, D. Poindexter, and M. Steger, IEEE Electron Device Letters, Vol. 14, No. 8, August, 1993, the corner device can even dominate on-currents in applications such as DRAM that require narrow channel widths to achieve high density. This parallel current-carrying corner device becomes the dominant MOSFET contributor to standby current in low standby power logic applications and to leakage in DRAM cells. Furthermore, there exists concern that the enhanced electric fields due to field crowding at the comer impact dielectric integrity.
A paper, "Behavior of an NMOS Trench-Isolated Corner Parasitic Device at Low Temperature," by D. Foty, J. Mandelman, and T. Furukawa, Proceedings of the Electrochemical Society Meeting, October, 1989, suggests that the corner parasitic device does not improve with decreasing temperature nearly as much as the planar subthreshold slope. Thus, the comer parasitic device may be more of a problem at low temperature than the planar device.
This comer leakage problem has commonly been controlled with an increased threshold tailor implant dose, but this can degrade device performance. Thus, alternate schemes for controlling the corner are needed.
A paper, "A Deep-Submicron Isolation Technology with T-shaped Oxide (TSO) Structure," by T. Ishijima et al., Proceedings of the IEDM, 1990, p. 257, addresses the problem of trench sidewall inversion. This paper teaches the use of a pair of aligned photomasks to form a T-shaped oxide adjacent the comer of an isolation trench and the use of a channel stop boron implant along sidewalls of the trench. The structure moves the device away from the trench sidewall and provides boron to raise the Vt along that sidewall. However, isolation is enlarged when photomask alignment tolerances are included in this two-mask-and-implant scheme, making this solution undesirable. While commonly assigned copending patent application, "A Corner Protected Shallow Trench Isolation Device," by M. M. Armacost et al., provides a scheme to protect the corner while not enlarging the isolation, the root problem of corner sharpening and oxide thinning remains. Thus, an improved means to control the corner parasitic is needed and is provided by the following invention.